`timescale 1ps / 1ps
module TestBench;

	// Inputs
	reg clk;
	reg rst;

	// Instantiate the Unit Under Test (UUT)
	mips uut (
		.clk(clk), 
		.rst(rst)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		#7
		rst = 0;
		// Add stimulus here

	end
      
	always #5 begin
		clk = ~clk;
	end
endmodule

